With the ever increasing edge rate of the output drivers in programmable integrated circuits (PICs), ground bounce or ringing on the output of a device has become a significant problem in both the programming/ testing and the usage of PICs. The ground bounce problem is exacerbated by a noisy wafer sort environment, poorly designed programmer circuits and system board layouts that are carelessly designed.
It is known that many existing programmer circuits are very poorly grounded in use, and when verified, a PIC is more likely to fail. Hence, to provide a mode in which the output signal speed can be reduced which will also reduce the likelihood of "snap back" is highly desirable. Snap back occurs due to a large voltage difference present between the input pin and negatively going ground. In addition, during normal operation output overshoots/undershoots that are due to ringing should be minimized to prevent device failures. Finally, many customers want to be given the opportunity to select the output in which the signal speed is to be reduced. In many cases, it is not important that all of the output signals be high speed outputs.
A programmable integrated circuit normally requires that a "super voltage" be provided at one of its input pins to cause the device enter into an "Edit" mode where the EEPROM array can be erased, programmed, and verified. During the verify cycle, where all of the outputs of this device can switch from high to low simultaneously, the ground bounce can cause the device to fail to verify correctly and/or cause the high voltage pin to snap back due to the large voltage difference between the pin and the undershooting ground. This situation is especially severe in the wafer sort and third party programmer environment where ground integrity is fairly weak.
In the normal logic mode output overshoots/undershoots and ringing can cause the device that it is driving to double clock and fail. Another possible failure mechanism in logic mode is that the ground bounce is fed back into the input of the device thereby causing the device to oscillate.
The present invention provides circuitry that minimizes the above-mentioned problems in a high speed programmable integrated circuit.